This invention relates to digital logic circuits on semiconductor chips; and more particularly, it relates to means within such circuits for reducing switching noise.
In the prior art it is common to construct over two thousand digital logic gates on a single semiconductor chip. Those gates are often interconnected on the chip to simultaneously perform several different logic functions. Each digital signal that represents a completed logic function is then sent off of the chip through a respective output driver. Usually the number of output drivers on a single chip is at least twenty.
When the logic signals to some of the output drivers switch from one state to another, switching noise is generated on the voltage buses on the chip. That noise is then coupled by parasitic resistive and capacitive elements to the remaining output drivers which at the time are not supposed to switch. However, if the noise becomes too large, it will cause glitches in the signals from the output drivers and that in turn can cause system malfunctions. Thus it is highly desirable to circumvent this noise problem.
One factor which affects the magnitude of switching noise is the speed at which the logic signals from the output drivers change state. Switching noise increases as switching speed gets faster; and one approach in the prior art to decrease switching noise was to add capacitors across the output drivers to slow down the speed at which they switched. However, such an approach is unattractive because it limits the overall performance of the chip. A primary goal of many digital circuits (e.g., digital computers) is to operate as fast as possible; and intentionally slowing down the switching speed of the output drivers directly limits from that goal.
Another approach in the prior art to reducing switching noise was to reduce the inductance of the chip's voltage buses. Part of that inductance is caused by the voltage pins on the package which encapsulates the chip; and it is reduced by providing several voltage pins on the package in parallel. However, by allocating several pins to voltage, the total number of pins that are available for carrying logic signals is reduced; and often a chip designer wants all the logic signal pins he can get. Further, other components (such as bonding wire between the chip and the package and conductive traces on the package between the bonding wire and the pins) add to the voltage bus inductance, and they remain even if several voltage pins are placed in parallel.
Accordingly, a primary object of the invention is to provide a module for use with an integrated circuit that substantially reduces the circuit's susceptibility to switching noise without slowing the circuit's switching speed and without requiring multiple parallel voltage pins.